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For verilog HDL simulation, you can use ghdl tool. This a tool that is used to develop a metal layer and connect a netlist in the VLSI fabrication technology. It is basically a maze router.

Verilator is the best and fastest free VHDL simulator tool. It compiles synthesized verilog and SystemVerilog, PSL, & Synthesis assertions into SystemC code or C++. Although this tool is designed for big projects requiring fast simulation performance, it also suited to generate executable models of CPUs for embedded software design purpose.

Veena, you can either use verilator or chipvault. This tool is used to organise VHDL. ChipVault displays enables rapid design navigation and editor launching process. It also offers hooks for conducting bottom-up including synthesis, launching RTL compilers, block generation and instantiation, etc.

Thank you so much for the suggestions guys